Semiconductor device

ABSTRACT

Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, fowling a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application is a continuationapplication of U.S. patent application Ser. No. 15/381,135; filed onDec. 16, 2016 with the U.S. Patent and Trademark Office, which claimsthe benefit of Korean Patent Application No. 10-2016-0050200 filed onApr. 25, 2016 in the Korean Intellectual Property Office, thedisclosures of which are hereby incorporated herein by reference intheir entireties.

BACKGROUND OF THE INVENTIVE CONCEPT 1. Field of the Inventive Concept

The present inventive concept relates to methods for manufacturing asemiconductor device.

2. Description of the Related Art

As semiconductor devices are highly integrated and their patterns becomeminute, various attempts have been made to manufacture the semiconductordevices with improved characteristics. In particular, various methodsfor manufacturing a landing pad that supports eccentricity, whileensuring a stable contact between an upper conductor and a lowerconductor such as a bit line or a storage electrode in a structure suchas a memory cell having a honeycomb structure may be performed.

SUMMARY OF THE INVENTIVE CONCEPT

An aspect of the present inventive concept provides methods formanufacturing a semiconductor device that allows a self-alignment to beperformed using a previously patterned fence and allows a lithographyprocess to be reduced in forming a landing pad.

Another aspect of the present inventive concept provides methods formanufacturing a semiconductor device that allows a process margin to beensured by partially etching the landing pad.

However, aspects of the present inventive concept are not restricted tothe one set forth herein. The above and other aspects of the presentinventive concept will become more apparent to one of ordinary skill inthe art to which the present inventive concept pertains by referencingthe detailed description of the present inventive concept given below.

According to an aspect of the present inventive concept, there isprovided a method for manufacturing a semiconductor device includingforming a gate line extending in a first direction in a substrate, andan impurity region on a side surface of the gate line, forming aninsulating film pattern on the substrate, the insulating film patternextending in the first direction and comprising a first through-hole forexposing the impurity region, forming a barrier metal layer on the firstthrough-hole, forming a conductive line contact that fills the firstthrough-hole and is electrically connected to the impurity region,forming a first mask pattern on the conductive line contact and theinsulating film pattern, the first mask pattern extending in a seconddirection different from the first direction and comprising a firstopening, forming a landing pad by performing a photolithography processusing the first mask pattern, and removing corners by partially etchingthe barrier metal layer.

According to another aspect of the present inventive concept, there isprovided a method for manufacturing a semiconductor device includingforming a gate line extending in a first direction in a substrate, andan impurity region on a side surface of the gate line, forminginsulating film patterns extending in the first direction on thesubstrate, forming a conductive line contact in a first through-holebetween the insulating film patterns, using the insulating film patternsas a negative pattern, forming a barrier metal layer on the firstthrough-hole, forming a first mask pattern on the insulating filmpattern, the first mask pattern extending in a second directiondifferent from the first direction and comprising a first opening,forming a landing pad by performing a photolithography process, usingthe first mask pattern as a positive pattern, and removing corners bypartially etching the barrier metal layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects and features of the present inventiveconcept will become more apparent by describing in detail exampleembodiments thereof with reference to the attached drawings, in which:

FIG. 1 is a plan view for illustrating a semiconductor device accordingto some embodiments of the present inventive concept;

FIGS. 2 to 10 are cross-sectional views for illustrating methods formanufacturing a semiconductor device according to some embodiments ofthe present inventive concept;

FIG. 11 is a perspective view for explaining a semiconductor deviceaccording to some embodiments of the present inventive concept;

FIG. 12 is a top view for illustrating the semiconductor device of FIG.11;

FIGS. 13 to 15 are cross-sectional views illustrating methods formanufacturing a semiconductor device according to some other embodimentsof the present inventive concept;

FIGS. 16 and 17 are perspective views for illustrating the semiconductordevice of FIGS. 13 to 15;

FIGS. 18 to 20 are cross-sectional views illustrating methods formanufacturing a semiconductor device according to some other embodimentsof the present inventive concept;

FIGS. 21 to 23 are cross-sectional views illustrating methods formanufacturing a semiconductor device according to some other embodimentsof the present inventive concept; and

FIGS. 24 to 26 are exemplary semiconductor systems to which thesemiconductor devices according to some embodiments of the presentinventive concept are applicable.

DETAILED DESCRIPTION OF THE INVENTIVE CONCEPT

Embodiments will be described in detail with reference to theaccompanying drawings. The inventive concept, however, may be embodiedin various different forms, and should not be construed as being limitedonly to the illustrated embodiments. Rather, these embodiments areprovided as examples so that this disclosure will be thorough andcomplete, and will fully convey the concept of the inventive concept tothose skilled in the art. Accordingly, known processes, elements, andtechniques are not described with respect to some of the embodiments ofthe inventive concept. Unless otherwise noted, like reference numeralsdenote like elements throughout the attached drawings and writtendescription, and thus descriptions will not be repeated. In thedrawings, the sizes and relative sizes of layers and regions may beexaggerated for clarity.

It will be understood that, although the terms “first”, “second”,“third”, etc., may be used herein to describe various elements,components, regions, layers and/or sections, these elements, components,regions, layers and/or sections should not be limited by these terms.These terms are only used to distinguish one element, component, region,layer or section from another region, layer or section. Thus, a firstelement, component, region, layer or section discussed below could betermed a second element, component, region, layer or section withoutdeparting from the teachings of the inventive concept.

Spatially relative terms, such as “beneath”, “below”, “lower”, “under”,“above”, “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. It will beunderstood that the spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the figures. For example, if the device inthe figures is turned over, elements described as “below” or “beneath”or “under” other elements or features would then be oriented “above” theother elements or features. Thus, the example terms “below” and “under”can encompass both an orientation of above and below. The device may beotherwise oriented (rotated 90 degrees or at other orientations) and thespatially relative descriptors used herein interpreted accordingly. Inaddition, it will also be understood that when a layer is referred to asbeing “between” two layers, it can be the only layer between the twolayers, or one or more intervening layers may also be present.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the inventiveconcept. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items. Also, the term “exemplary” is intended to referto an example or illustration.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to”, “coupled to”, or “adjacent to” anotherelement or layer, it can be directly on, connected, coupled, or adjacentto the other element or layer, or intervening elements or layers may bepresent. In contrast, when an element is referred to as being “directlyon,” “directly connected to”, “directly coupled to”, or “immediatelyadjacent to” another element or layer, there are no intervening elementsor layers present.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this inventive concept belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and/orthe present specification and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

Advantages and features of the present disclosure and methods ofaccomplishing the same may be understood more readily by reference tothe following detailed description of preferred embodiments and theaccompanying drawings.

FIG. 1 is a plan view for illustrating a semiconductor device accordingto some embodiments of the present inventive concept.

Referring to FIG. 1, a semiconductor device according to someembodiments of the present inventive concept includes a fence 130 and asecond contact 137 b.

The fence 130 includes an insulating material, e.g., SiN. The fence 130is formed to extend in a first direction DR1, and is formed on a gateline 108 that includes a buried gate structure, as described below inconjunction with FIG. 7. The fence 130 serves as a separation film andmay also serve to self-align the second contact 137 b in a firstdirection DR1.

The second contact 137 b includes a honeycomb structure 140 a, and mayserve as a landing pad. The second contact 137 b as the landing pad mayhave a parallelogram shape in some embodiments of the present inventiveconcept.

Therefore, it is possible to form the fence 130 and a first mask pattern155 disposed between first openings 155 b extending in one direction onthe second contact 137 b. Here, the one direction may form an acuteangle, e.g., 60° with the first direction DR1. Further, the firstopenings 155 b includes a line shape, and the one direction may form anacute angle with the first direction DR1. Specifically, the line shapemay include an oblique line shape.

Such a landing pad of a parallelogram shape may be formed by performinga photolithography process using the first mask pattern 155. Thus, thelanding pad according to some embodiments of the present inventiveconcept may be self-aligned in the first direction DR1 using thepreviously patterned fence 130, and thereafter, the landing pad may beformed simply by a single photolithography process using the first maskpattern 155. That is, such a fence 130 may be used as a negative patternfor self-aligning the landing pad in the first direction DR1, and thefirst mask pattern 155 may be used as a positive pattern in aphotolithography process for forming the landing pad in a parallelogramshape. Thus, it is possible to reduce the cost of process.

Meanwhile, the shape of the second contact 137 b as the landing pad insome other embodiments of the present inventive concept may be definedby the first mask pattern 155 disposed between first openings 155 d(FIG. 18) of a waveform shape, and the shape thereof may also be definedby the first mask pattern 155 disposed between first openings 155 f(FIG. 22) having a line shape extending in one direction.

This will be described in detail later with reference to FIGS. 13 to 23.

Hereinafter, methods for manufacturing a semiconductor device accordingto some embodiments of the present inventive concept will be describedwith reference to FIGS. 2 to 10.

FIGS. 2 to 10 are cross-sectional views for illustrating methods formanufacturing a semiconductor device according to some embodiments ofthe present inventive concept.

Referring to FIG. 2, a semiconductor device 1 includes a substrate 100,a bit line 90 and a gate line 108.

The substrate 100 includes an impurity region 104, and the impurityregion 104 may be formed between the gate lines 108 formed in thesubstrate 100. Further, the impurity region 104 may include a source anda drain.

The gate line 108 extends in the first direction DR1, and is formed bybeing buried in the substrate 100. The bit line 90 extends in a seconddirection DR2, and is formed on the substrate 100. Specifically, the bitline 90 is formed to intersect with the gate line 108, and the seconddirection DR2 may be perpendicular to the first direction DR1.

Referring to FIGS. 2 and 3, a gate line 108 extending in the firstdirection DR1 is formed in the substrate 100, and an impurity region 104is formed on the side surface of the gate line 108.

Specifically, in order to form the gate line 108 including the buriedgate structure, a trench 107 is formed in an element isolation film 105.The trench 107 may be formed using an etching process, and for example,a lithography process and a dry etching process may be included. Afterthe etching process, a gate conductive layer 108 a is formed in thetrench 107. The gate conductive layer 108 a may include, but not limitedto, polysilicon. The gate conductive layer 108 a is left only in thelower portion of the trench 107 through the etching process. The etchingprocess may include an etch-back process. After the etch-beck process, agate metal layer 108 b is formed on the substrate 100 including the gateconductive layer 108 a. The gate metal layer 108 b may include, but notlimited to, Ti, Ta, TiN, TaN, W, Wn and/or WSi.

After forming the gate metal layer 108 b, a CMP process is performeduntil the upper surface of the substrate 100 is exposed. The gateconductive layer 108 a and the gate metal layer 108 b are sequentiallyformed in the trench 107 by the CMP process, and a buried gate structureis completed.

The impurity region 104 is a region formed on the top of an activeregion 103 and may include a source and a drain, but it is not limitedthereto. For example, the impurity region 104 may be formed between thegate lines 108.

Referring to FIG. 4, the formation of the insulating film pattern mayinclude formation of a gate hard mask layer 110, a sacrificial film 115and an interlayer insulating film 120.

Specifically, the gate hard mask layer 110 may be formed on thesubstrate 108 b formed with the gate metal layer 100. That is, a gatehard mask layer 110 that overlaps the gate line 108 is formed.

The sacrificial film 115 may be formed between the gate hard mask layers110. The sacrificial film 115, for example, may include, but not limitedto, a nitride film. Specifically, the sacrificial film 115 may be formedon the substrate 100 including the patterned gate hard mask layer 110.After forming the sacrificial film 115, the CMP process is performeduntil the top surface of the gate hard mask layer 110 is exposed.

After forming the sacrificial film 115, the interlayer insulating film120 is formed on the sacrificial film 115 and the gate hard mask layer110. The interlayer insulating film 120, for example, may include, butnot limited to, an oxide layer.

Referring to FIG. 5, a shielding film 123 is formed on the interlayerinsulating film 120.

For example, the shielding film 123 may include, but, not limited to, anoxide film or a polysilicon film. The shielding film 123 may remove aninterference signal generated in the semiconductor device and/or mayblock the interference signal from being emitted to the outside.Further, the shielding film 123 may prevent the external interferencesignal from affecting the semiconductor device.

A second mask pattern 124 is formed on the shielding film 123. Thesecond mask pattern 124 extends in a first direction (DR1 in FIG. 1),and includes a second opening 124 a which overlaps the gate line 108.Specifically, the second mask pattern 124 may include a second opening124 a, and a region 124 b that defines the second opening 124 a.

Referring to FIG. 6, a second through-hole 125 that penetrates theshielding film 123, the interlayer insulating film 120 and the gate hardmask layer 110 is formed.

Specifically, the formation of the second through-hole 125 may includeremoval of the shielding film 123, the interlayer insulating film 120and the gate hard mask layer 110, using the second mask pattern 124 asan etching mask. The gate line 108 is exposed by the second through-hole125. That is to say, the second through-hole 125 exposes the gate metallayer 108 b. The second through-hole 125, for example, may be formedusing one of the wet etching, the dry etching and a combination thereofAfter performing the etching process, the second mask pattern 124 isremoved.

Referring to FIG. 7, the fence 130 is formed by filing the secondthrough-hole 125 with an insulating material.

An insulating material for forming the fence 130, for example, mayinclude SiN, may have high etching selectivity over the shielding film123 and the interlayer insulating film 120. Furthermore, the fence 130not only may serve as a separation film, but may also serve toself-align the first through-hole 135 in the first direction (DR1 inFIG. 2).

Referring to FIG. 8, after forming the fence 130, the shielding film123, the interlayer insulating film 120, the sacrificial film 115, andthe gate hard mask layer 110 are removed to form the first through-hole135.

Specifically, the interlayer insulating film 120 and the shielding film123 are etched. The etching process is performed using the fence 130 asa mask, and may include a wet etching process. For example, the etchingrates of the interlayer insulating film 120 and the shielding film 123for an etchant used in the wet etching may be larger than the etchingrate of the fence 130 for the etchant used in the wet etching.Specifically, since the etching rate of the fence 130 is very slow, thefence 130 is left without being etched, while the interlayer insulatingfilm 120 and the shielding film 123 are etched. After etching theinterlayer insulating film 120 and the shielding film 123, the gate hardmask layer 110 and the sacrificial film 115 are etched. For example, thegate hard mask layer 110 and the sacrificial film 115 may be etched,using the fence 130 as a mask. At this time, the etching process isperformed to a depth at which the gate metal layer 108 b is partiallyexposed. This allows the first contact 137 a formed in the next processto connect the gate line 108 and the bit line (90 in FIG. 2).

Referring to FIG. 9, barrier metal layers 145 are formed along the sidesurfaces of the fence 130. In some embodiments of the present inventiveconcept, the barrier metal layers 145 may be conformally formed alongthe side surfaces of the fence 130. Meanwhile, in some embodiments ofthe present inventive concept, the barrier metal layers 145 may include,but not limited to, Ti, Ta, TiN, TaN, W, Wn and/or WSi.

Referring to FIG. 10, the first through-hole 135 formed with the barriermetal layers 145 is filled to form a conductive line contact 137 that iselectrically connected to the impurity region 104.

Specifically, the formation of the conductive line contact 137 mayinclude formation of the first contact 137 a that partially fills thefirst through-hole 135, and formation of the second contact 137 b on thefirst contact 137 a. For example, the first contact 137 a may include agate bit line contact pad. Further, the first contact 137 a may serve toconnect the gate line 108 and the bit line 90. The second contact 137 bmay include a landing pad line. Further, the second contact 137 b mayinclude, but is not limited to, one of a metal film, a polysilicon film,a laminated structure of an epitaxial silicon film and/or a polysiliconfilm using an optional epitaxial growth, and a laminated structure of anepitaxial silicon film and a metal film using the optional epitaxialgrowth.

The conductive line contact 137 including the first contact 137 a andthe second contact 137 b may be self-aligned to the fence 130. That is,the conductive line contact 137 may be self-aligned to the fence 130 inthe first direction (DR1 in FIG. 9).

FIG. 11 is a perspective view for illustrating a semiconductor deviceaccording to some embodiments of the present inventive concept, and FIG.12 is a top view for illustrating the semiconductor device of FIG. 11.

Referring to FIGS. 11 and 12, the self-alignment of the second contact137 b to the fence 130 in the first direction DR1 can be checked in adirection different from FIG. 10.

FIGS. 13 to 15 are cross-sectional views illustrating methods formanufacturing a semiconductor device according to some other embodimentsof the present inventive concept, and FIGS. 16 and 17 are perspectiveviews for illustrating the semiconductor device of FIGS. 13 to 15.

Referring to FIGS. 13 to 15, a barrier metal layer 145 a formed alongthe second contact 137 b of the landing pad line is partially etched toremove the corner thereof. In some embodiments of the present inventiveconcept, the etching may include the wet etching.

Specifically, as illustrated in FIG. 13, a fence 130 and a first maskpattern 155 can be formed on the top surface of the semiconductor deviceas illustrated in FIGS. 11 and 12, and the first mask pattern 155disposed between first openings 155 b extending in one direction on thesecond contact 137 b. Here, the one direction may form an acute angle,e.g., 60° with the first direction DR1. Further, the first openings 155b includes a line shape, and the one direction may form an acute anglewith the first direction DR1. Specifically, the line shape may containan oblique line shape. In the case of the oblique line shape, the secondcontact 137 b may include a honeycomb structure 140 a.

Referring to FIG. 16 together, the barrier metal layers 145 a are formedalong both side surfaces of the fence 130.

Subsequently, referring to FIG. 13, the barrier metal layers 145 a arepartially on the basis of the fence 130 and the first mask pattern 155to remove their corners. Referring to FIG. 17 together, the barriermetal layers 145 a formed along the side surfaces of the fence 130 areetched in at least three directions. Thus, both side surfaces and thetop surfaces of the barrier metal layers 145 a are partially removed.That is, FIG. 14 corresponds to the cross-section taken along a line d₁of FIG. 17, and a hole 147 a provided after the removal of the barriermetal layer 145 a is formed in the region where there were the barriermetal layers 145 a in FIG. 13.

Subsequently, referring to FIG. 15, FIG. 15 corresponds to thecross-section of a line d₂ of FIG. 17, holes 147 a are formed on bothends of the region where there were the barrier metal layers 145 a inFIG. 13, and the barrier metal layers 145 a having a shape of a reducedsize are formed.

FIGS. 18 to 20 are cross-sectional views illustrating methods formanufacturing a semiconductor device according to some other embodimentsof the present inventive concept.

Referring to FIGS. 18 to 20, the barrier metal layers 145 c formed alongthe second contact 137 b of the landing pad line are partially etched toremove their corners. In some embodiments of the present inventiveconcept, the etching may include the wet etching.

Specifically, as illustrated in FIG. 18, the fence 130 and a first maskpattern 155 may be formed on the top surface of the semiconductor deviceas illustrated in FIGS. 11 and 12. The first mask pattern 155 includes afirst opening 155 d extending in a waveform shape on the second contact137 b. In the case of a waveform shape, the second contact 137 b mayinclude a honeycomb structure 140 a. Meanwhile, similar to thedescription of FIG. 13, the barrier metal layers 145 c are formed alongboth side surfaces of the fence 130.

Next, with reference to FIG. 19, the barrier metal layers 145 c arepartially etched on the basis of the fence 130 and the first maskpattern 155 to remove their corners. Similar to the description of FIG.14, the barrier metal layers 145 c formed along the side surfaces of thefence 130 are etched in at least three directions. Thus, both sidesurfaces and the top surface of the barrier metal layer 145 c arepartially removed. That is, similar to the description of FIG. 14, holes147 c provided after the removal of the barrier metal layers 145 c areformed in the regions of FIG. 18 where there were the barrier metallayers 145 c.

Next, with reference to FIG. 20, similar to the description of FIG. 15,holes 147 c are formed at both ends of the region where there were thebarrier metal layers 145 c in FIG. 18, and the barrier metal layers 145c having a shape of reduced size are formed.

FIGS. 21 to 23 are cross-sectional views illustrating methods formanufacturing a semiconductor device according to some other embodimentsof the present inventive concept.

Referring to FIGS. 21 to 23, a barrier metal layer 145 e formed alongthe second contact 137 b of the landing pad line is partially etched toremove its corner. In some embodiments of the present inventive concept,the etching may include the wet etching.

Specifically, as illustrated in FIG. 21, the fence 130 and the firstmask pattern 155 may be formed on the top surface of the semiconductordevice as illustrated in FIGS. 11 and 12. The first mask pattern 155disposed between first openings 155 f extending in one direction on thesecond contact 137 b. The one direction of the first openings 155 f maybe a second direction DR2 perpendicular to the first direction DR1. Inthis case, the second contact 137 b may include a square structure 140 brather than a honeycomb structure 140 a. Meanwhile, similar to thedescription of FIG. 13, the barrier metal layers 145 e are formed alongboth side surfaces of the fence 130.

Next, with reference to FIG. 22, the barrier metal layers 145 e arepartially etched on the basis Of the fence 130 and the first maskpattern 155 to remove their corners. Similar to the description of FIG.14, the barrier metal layers 145 e formed along the side surfaces of thefence 130 are etched in at least three directions. Thus, the both sidesurfaces and the top surfaces of the barrier metal layers 145 e arepartially removed. That is, similar to the description of FIG. 14, holes147 e provided after the removal of the barrier metal layers 145 e areformed in regions where there were the barrier metal layers 145 e inFIG. 21.

Next, with reference to FIG. 23, similar to the description of FIG. 15,holes 147 e are formed at both ends in the regions where there were thebarrier metal layers 145 e in FIG. 21, and the barrier metal layers 145e having a reduced size are formed.

Thus, the landing pad according to some embodiments of the presentinventive concept may be self-aligned in the first direction DR1 usingthe fence 130 patterned in advance, and may be farmed only by a singlephotolithography process using the first mask pattern 155. That is, sucha fence 130 may be used as a negative pattern for self-aligning thelanding pad in the first direction DR1, and the first mask pattern 155may be used as a positive pattern. Thus, it is possible to reduce theprocess cost.

Furthermore, by partially etching the barrier metal layer 145 formedalong the second contact 137 b of the landing pad line to remove itscorner, a process margin may be sufficiently if needed.

FIGS. 24 to 26 are diagrams illustrating examples of a semiconductorsystem to which the semiconductor devices according to some embodimentsof the present inventive concept can be applied.

FIG. 24 illustrates a tablet personal computer (PC) 1200, FIG. 25illustrates a notebook computer 1300, and FIG. 26 illustrates a smartphone 1400. The semiconductor devices according to some embodiments ofthe present inventive concept may be used in the tablet PC 1200, thenotebook computer 1300, the smart phone 1400 and the like.

Further, it is obvious to a person skilled in the art that thesemiconductor devices according to some embodiments of the presentinventive concept may also be applied to other IC devices other thanthose set forth herein. That is, while only the tablet PC 1200, thenotebook computer 1300 and the smart phone 1400 have been describedabove as examples in which the semiconductor devices according to thisembodiment are usable, the application examples of the semiconductordevices according to some embodiments of the present embodiment are notlimited thereto. In some embodiments of the present inventive concept,the semiconductor apparatus may be provided as a computer, an UltraMobile PC (UMPC), a work station, a net-book computer, a personaldigital assistant (PDA), a portable computer, a wireless phone, a mobilephone, an e-book, a portable multimedia player (PMP), a portable gameconsole, a navigation device, a black box, a digital camera, a3-dimensional television set, a digital audio recorder, a digital audioplayer, a digital picture recorder, a digital picture player, a digitalvideo recorder, and/or a digital video player, among others.

While the present inventive concept has been particularly illustratedand described with reference to example embodiments thereof, it will beunderstood by those of ordinary skill in the art that various changes inform and detail may be made therein without departing from the spiritand scope of the present inventive concept as defined by the followingclaims. The example embodiments should be considered in a descriptivesense only and not for purposes of limitation.

What is claimed is:
 1. A semiconductor device comprising: a plurality ofgate lines extending in a first direction in a substrate; an impurityregion formed between the plurality of gate lines; a plurality ofinsulation film patterns on the plurality of gate lines, extending inthe first direction; a conductive line contact formed between theplurality of insulation film patterns and is electrically connected tothe impurity region; and a first mask pattern formed on the conductiveline contact and the plurality of insulating film patterns, extending ina second direction that is different from the first direction, whereinthe conductive line contact includes a landing pad formed by performinga photolithography process using the first mask pattern.
 2. Thesemiconductor device of claim 1, further comprising: a barrier metallayer formed between the plurality of insulation film patterns and theconductive line contact, wherein a hole is formed between the barriermetal layer and the first mask pattern.
 3. The semiconductor device ofclaim 1, wherein the first mask pattern comprises an opening thatextends in an oblique line shape.
 4. The semiconductor device of claim1, wherein the first mask pattern comprises an opening that extends in awaveform shape.
 5. The semiconductor device of claim 1, wherein thefirst mask pattern comprises an opening that extends in a perpendiculardirection.
 6. The semiconductor device of claim 1, wherein the firstdirection forms an acute angle with the second direction.